The present invention relates to memory management and, more specifically, to a latency-agnostic memory controller.
Generally, a memory controller handles reading from and writing to computer memory. More specifically, a memory controller reads and writes to one kind of memory, dynamic random-access memory (DRAM). DRAM uses a deterministic protocol with fixed-access latency and, as a result, yields predictability with respect to response times. A memory controller inserts requests to access memory into a first-in-first-out (FIFO) queue and addresses those requests in order, with responses being returned in order due to the fixed-access latency. Recently, however, there have been efforts to combine multiple types of memory on a single computer.